1. Field of the Invention
The present invention relates to a high-efficiency voltage booster circuit operating at very low supply voltage.
Though applicable in particular to switching regulators featuring N-channel power MOS transistors which require a high gate potential for proper operation, the present invention may also be applied to any device comprising a pass MOS transistor which operates at very low supply voltage. In particular, the present invention may be applied to all MOS and combined BJT/MOS technologies with threshold voltages above or comparable with the supply voltage. For example, the present invention may be applied to devices used in pagers, cordless systems, radio-controlled systems and Local Area Networks which are supplied by a single low-voltage battery and which, according to present standards, must operate at supply voltages of 800 mV or at most 900 mV.
2. Discussion of the Related Art
As is known, the physical performance of switching regulators featuring MOS transistors for controlling the current in the inductor should simulate, as closely as possible, that of an ideal switch. That is, ideally, the MOS transistor should present zero resistance between the drain and source when on. In actual fact, however, this never occurs. The resistance of the transistor when on equals R.sub.ds,on, and must be minimized as much as possible to reduce the voltage drop and power dissipation of the transistor to achieve a good degree of efficiency of the regulator.
As is known, the voltage drop of the transistor is inversely proportional to both its area and overdrive (i.e. the excess gate-source voltage in relation to the turn-on threshold voltage of the transistor). Therefore, if a limited area of the MOS transistor is required, as in the case of currently used integrated devices, which are necessarily increasingly smaller and mounted in very small packages, the only alternative is to work on the overdrive voltage of the transistor (V.sub.ov =V.sub.gs -V.sub.th). That is, for the switching regulator to operate properly, a high overdrive must be assured.
On the other hand, a high overdrive also means a high gate-source voltage V.sub.gs, which poses problems in the case of the circuits with low supply voltages mentioned previously. This is because the minimum threshold voltages achievable by the best technologies currently available are comparable with, if not less than, the low supply voltages required. Nor is it possible, at the low supply voltages considered, to use diodes as unilateral switches.
As such, recourse must be made to voltage boosters or pumps capable of generating, from a low supply voltage, a higher voltage for gate driving MOS transistors.
Known voltage boosters include what are referred to as Cockroft-Walton second or higher-order multipliers. These multipliers operate in accordance with a succession of steps comprising: charging a capacitor to a voltage correlated to the supply voltage; pulling up one terminal of the capacitor; and connecting the other terminal of the capacitor to an output via controlled switches to achieve an output voltage higher than the supply voltage.
FIG. 1 shows one example of a third-order multiplier 1 comprising three PNP transistors 2, 3 and 4 and two NPN transistors 5 and 6 connected between a supply line at V.sub.dd and ground. More specifically, transistor 2 has an emitter terminal connected to the supply voltage V.sub.dd, a base terminal connected to the base terminal of transistor 3 and to the emitter terminal of transistor 4, and a collector terminal connected to the collector terminal of transistor 5, to the base terminal of transistor 4 and to the base terminal of transistor 6. Transistor 3 has an emitter terminal connected to the supply voltage V.sub.dd, and a collector terminal connected to a node 8. Transistor 4 has a collector terminal which is grounded. Transistor 5 has a base terminal defining an input 9 at which it receives a turn-on signal V.sub.1, and an emitter terminal grounded via a resistor 10. Transistor 6 has an emitter terminal which is grounded. Circuit 1 also comprises two capacitors 12, 13, each having one terminal 15, 16, respectively, which defines an input for respective push-pull digital control signals S1, S2, and the other terminal A, B of each, respectively, which is connected to a respective terminal of a chain of diodes 17, 18, 19. More specifically, diode 17 is connected at the anode to node 8, and at the cathode to terminal A and to the anode of diode 18. The cathode of diode 18 is connected to terminal B and to the anode of diode 19, and the cathode of diode 19 forms an output terminal 20 which outputs a voltage O.
Components 2-6 and 10 form an input stage for transferring the supply voltage V.sub.dd to node 8 when V.sub.1 is high. In this condition, it is assumed S1 is low and S2 is high at an instant t.sub.0, so that a potential V.sub.A at terminal A equals: EQU V.sub.A (t.sub.0)=V.sub.dd -V.sub.cesat,3 -V.sub.d,17
where V.sub.cesat,3 is the collector-emitter voltage drop across transistor 3 when saturated; and V.sub.d,17 is the voltage drop across diode 17.
A potential V.sub.B at terminal B, on the other hand, equals: EQU V.sub.B (t.sub.0)=V.sub.dd -V.sub.cesat,3 -V.sub.d,17 -V.sub.d,18
where V.sub.d,18 is the voltage drop across diode 18. For example, if voltage V.sub.dd equals 5 V, if V.sub.cesat,3 equals 0.3 V, and if the voltage drop of the diodes equals 0.7 V, then V.sub.A (t.sub.0)=4 V and V.sub.B (t.sub.0)=3.3 V.
At an instant t.sub.1, S1 switches to high (V.sub.dd) and S2 to low, and, since capacitor 12 is already charged, terminal A is brought to potential: EQU V.sub.A (t.sub.1)=V.sub.A (t.sub.0)+V.sub.dd
diode 17 turns off, and terminals B and 20 are brought to potential: EQU V.sub.B (t.sub.1)=V.sub.A (t.sub.1)-V.sub.d18 EQU V.sub.20 (t.sub.1)=V.sub.B (t.sub.1)-V.sub.d19
where V.sub.d,19 is the voltage drop across diode 19. In the example shown, V.sub.A (t.sub.1)=9 V, V.sub.B (t.sub.1)=8.3 V and V.sub.20 (t.sub.1)=7.6 V.
At an instant t.sub.2, S1 switches back to low and S2 to high (V.sub.dd), diode 18 turns off, and the potentials at terminals A, B and 20 equal: EQU V.sub.A (t.sub.2)=V.sub.A (t.sub.0)=4 V EQU V.sub.B (t.sub.2)=V.sub.B (t.sub.1)+V.sub.dd =13.3 V EQU V.sub.20 (t.sub.2)=V.sub.B (t.sub.2)-V.sub.d19 =12.6 V
As can be seen, the loss in efficiency of the circuit of FIG. 1 is considerable, mainly because of the voltage drop across diodes 17-19. This prevents the circuit from being used in the presence of very low supply voltages (800 mV mentioned previously) at which it is not even possible to charge capacitors 12 and 13 because of the voltage drop across diodes 17, 18.